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The R3000A

The heart of the PSX is a slightly modified R3000A CPU from MIPS and LSI. This is a 32-bit Reduced Instruction Set Controller (RISC) processor that clocks at 33.8688 MHz. It has an operating performance of 30 million instructions per second. In addition, it has an internal instruction cache of 4 KB, a data cache of 1 KB and has a bus transfer rate of 132 MB/sec. It has internally one Arithmetic/Logic unit (ALU), One shifter, and totally lacks an FPU or floating point unit. The R3000A is configured for litle-endian byte order and defines a word as 32 bits, a half-word as 16 bits, and a byte as 8 bits.

The PSX has two coprocessors, cop0, the System Control coprocessor, and cop2, the GPU or Graphics Processing Unit. These are covered later on in this document.

Instruction cache

The PSX's R3000A contains 4 KB of instruction cache. The instruction cache is organized with a line size of 16 bytes. This should achieve hit rate of around 80%. The cache is implemented using physical address and tags, as opposed to virtual ones.

Data cache

The PSX's R3000A incorporates an on-chip data cache of 1 KB, organized as a line size of 4 bytes (one word). This also should achieve hit rates of 80% in most applications. This also is a directly mapped physical address cache. The data cache is implemented as a write through cache, to maintain that the main memory is the same as the internal cache. In order to minimize processor stalls due to data write operations, the bus interface unit uses a 4-deep write buffer which captures address and data at the processor execution rate, allowing it to be retired to main memory at a much slower rate without impacting system performance.

32-bit architecture

The R3000A uses thirty-two 32-bit registers, a 32-bit program counter, and two 32-bit registers for multiply/divide functions. The following table lists the registers by register number, name, and usage.

General Purpose Registers
Register number	Name	Usage
`R0`	ZR	Constant Zero
`R1`	AT	Reserved for the assembler
`R2`-`R3`	V0-V1	Values for results and expression evaluation
`R4`-`R7`	A0-A3	Arguments
`R8`-	T0-T7	Temporaries (not preserved across call)
`R16`-`R23`	S0-S7	Saved (preserved across call)
`R24`-`R25`	T8-T9	More temporaries (not preserved across call)
`R26`-`R27`	K0-K1	Reserved for OS Kernel
`R28`	GP	Global Pointer
`R29`	SP	Stack Pointer
`R30`	FP	Frame Pointer
`R31`	RA	Return address (set by function call)

Multiply/divide result registers and program counter
Name	Description
`HI`	Multiplication 64-bit high result or division remainder
`LO`	Multiplication 64-bit low result or division quotient
`PC`	Program Counter

Even though all general purpose registers have different names, they are all treated the same except for two. The R0 (ZR) register is hardwired as zero. The Second exception is R31 (RA) which is used at a link register when link or jump routines are called. These instructions are used in subroutine calls, and the subroutine return address is placed in register R31. This register can be written to or read as a normal register in other operations.

The R3000A instruction set

The instruction encoding is based on the MIPS architecture. This means that there are three types of instruction encoding.

I-Type (Immediate)
`op`	`rs`	`rt`	`immediate`

J-Type (Jump)
`op`	`target`

R-Type (Register)
`op`	`rs`	`rt`	`rd`	`shamt`	`funct`

Where:

`op`	is a 6-bit operation code
`rs`	is a five bit source register specifier
`rt`	is a 5-bit target register or branch condition
`immediate`	is a 16-bit immediate, or branch or address displacement
`target`	is a 26-bit jump target address
`rd`	is a 5-bit destination register specifier
`shamt`	is a 5-bit shift amount
`funct`	is a 6-bit function field

The R3000A instruction set can be divided into the following basic groups:

Load/Store instructions move data between memory and the general registers. They are all encoded as "I-Type" instructions, and the only addressing mode implemented is base register plus signed, immediate offset. This directly enables the use of three distinct addressing modes: register plus offset; register direct; and immediate.
Computational instructions perform arithmetic, logical, and shift operations on values in registers. They are encoded as either "R-Type" instructions, when both source operands as well as the result are general registers, and "I-Type", when one of the source operands is a 16-bit immediate value. Computational instructions use a three address format, so that operations don-t needlessly interfere with the contents of source registers.
Jump and Branch instructions change the control flow of a program. A Jump instruction can be encoded as a "J-Type" instruction, in which case the Jump target address is a paged absolute address formed by combining the 26-bit immediate value with four bits of the Program Counter. This form is used for subroutine calls. Alternately, Jumps can be encoded using the "R-Type" format, in which case the target address is a 32-bit value contained in one of the general registers. This form is typically used for returns and dispatches. Branch operations are encoded as "I-Type" instructions. The target address is formed from a 16-bit displacement relative to the Program Counter. The Jump and Link instructions save a return address in Register R31. These are typically used as subroutine calls, where the subroutine return address is stored into R31 during the call operation.
Co-Processor instructions perform operations on the co-processor set. Co-Processor Loads and Stores are always encoded as "I-Type" instructions; co-processor operational instructions have co-processor dependent formats. In the R3000A, the System Control Co-Processor (cop0) contains registers which are used in memory management and exception handling.
Special instructions perform a variety of tasks, including movement of data between special and general registers, system calls, and breakpoint operations. They are always encoded as "R-Type" instructions.

Instruction set summary

The following table describes The assembly instructions for the R3000A. Please refer to the next section for more detail about opcode encoding.

Load and Store Instructions
Instruction	Format and Description
Load Byte	LB `rt`, offset (base) Sign-extend 16-bit offset and add to contents of register base to form address. Sign-extend contents of addressed byte and load into `rt`.
Load Byte Unsigned	LBU `rt`, offset (base) Sign-extend 16-bit offset and add to contents of register base to form address. Zero-extend contents of addressed byte and load into `rt`.
Load Halfword	LH `rt`, offset (base) Sign-extend 16-bit offset and add to contents of register base to form address. Sign-extend contents of addressed byte and load into `rt`.
Load Halfword Unsigned	LHU `rt`, offset (base) Sign-extend 16-bit offset and add to contents of register base to form address. Zero-extend contents of addressed byte and load into `rt`.
Load Word	LW `rt`, offset (base) Sign-extend 16-bit offset and add to contents of register base to form address. Load contents of addressed word into register `rt`.
Load Word Left	LWL `rt`, offset (base) Sign-extend 16-bit offset and add to contents of register base to form address. Shift addressed word left so that addressed byte is leftmost byte of a word. Merge bytes from memory with contents of register `rt` and load result into register `rt`.
Load Word Right	LWR `rt`, offset (base) Sign-extend 16-bit offset and add to contents of register base to form address. Shift addressed word right so that addressed byte is rightmost byte of a word. Merge bytes from memory with contents of register `rt` and load result into register `rt`.
Store Byte	SB `rt`, offset (base) Sign-extend 16-bit offset and add to contents of register base to form address. Store least significant byte of register `rt` at addressed location.
Store Halfword	SH `rt`, offset (base) Sign-extend 16-bit offset and add to contents of register base to form address. Store least significant halfword of register `rt` at addressed location.
Store Word	SW `rt`, offset (base) Sign-extend 16-bit offset and add to contents of register base to form address. Store least significant word of register `rt` at addressed location.
Store Word Left	SWL `rt`, offset (base) Sign-extend 16-bit offset and add to contents of register base to form address. Shift contents of register `rt` right so that leftmost byte of the word is in position of addressed byte. Store bytes containing original data into corresponding bytes at addressed byte.
Store Word Right	SWR `rt`, offset (base) Sign-extend 16-bit offset and add to contents of register base to form address. Shift contents of register `rt` left so that rightmost byte of the word is in position of addressed byte. Store bytes containing original data into corresponding bytes at addressed byte.

Computational instructions

ALU Immediate Operations
Instruction	Format and Description
ADD Immediate	ADDI `rt`, `rs`, immediate Add 16-bit sign-extended immediate to register `rs` and place 32-bit result in register `rt`. Trap on two's complement overflow.
ADD Immediate Unsigned	ADDIU `rt`, `rs`, immediate Add 16-bit sign-extended immediate to register `rs` and place 32-bit result in register `rt`. Do not trap on overflow.
Set on Less Than Immediate	SLTI `rt`, `rs`, immediate Compare 16-bit sign-extended immediate with register `rs` as signed 32-bit integers. Result = 1 if `rs` is less than immediate; otherwise result = 0. Place result in register `rt`.
Set on Less Than Unsigned Immediate	SLTIU `rt`, `rs`, immediate Compare 16-bit sign-extended immediate with register `rs` as unsigned 32-bit intege`rs`. Result = 1 if `rs` is less than immediate; otherwise result = 0. Place result in register `rt`. Do not trap on overflow.
AND Immediate	ANDI `rt`, `rs`, immediate Zero-extend 16-bit immediate, AND with contents of register `rs` and place result in register `rt`.
OR Immediate	ORI `rt`, `rs`, immediate Zero-extend 16-bit immediate, OR with contents of register `rs` and place result in register `rt`.
Exclusive OR Immediate	XORI `rt`, `rs`, immediate Zero-extend 16-bit immediate, exclusive OR with contents of register `rs` and place result in register `rt`.
Load Upper Immediate	LUI `rt`, immediate Shift 16-bit immediate left 16-bits. Set least significant 16-bits of word to zeroes. Store result in register `rt`.

Three Operand Register-Type Operations
Instruction	Format and Description
Add	ADD `rd`, `rs`, `rt` Add contents of registers `rs` and `rt` and place 32-bit result in register `rd`. Trap on two's complement overflow.
ADD Unsigned	ADDU `rd`, `rs`, `rt` Add contents of registers `rs` and `rt` and place 32-bit result in register `rd`. Do not trap on overflow.
Subtract	SUB `rd`, `rs`, `rt` Subtract contents of registers `rt` and `rs` and place 32-bit result in register `rd`. Trap on two's complement overflow.
Subtract Unsigned	SUBU `rd`, `rs`, `rt` Subtract contents of registers `rt` and `rs` and place 32-bit result in register `rd`. Do not trap on overflow.
Set on Less Than	SLT `rd`, `rs`, `rt` Compare contents of register `rt` to register `rs` (as signed 32-bit integers). If register `rs` is less than `rt`, result = 1; otherwise, result = 0.
Set on Less Than Unsigned	SLTU `rd`, `rs`, `rt` Compare contents of register `rt` to register `rs` (as unsigned 32-bit integers). If register `rs` is less than `rt`, result = 1; otherwise, result = 0.
AND	AND `rd`, `rs`, `rt` Bit-wise AND contents of registers `rs` and `rt` and place result in register `rd`.
OR	OR `rd`, `rs`, `rt` Bit-wise OR contents of registers `rs` and `rt` and place result in register `rd`.
Exclusive OR	XOR `rd`, `rs`, `rt` Bit-wise Exclusive OR contents of registers `rs` and `rt` and place result in register `rd`.
NOR	NOR `rd`, `rs`, `rt` Bit-wise NOR contents of registers `rs` and `rt` and place result in register `rd`.

Shift Operations
Instruction	Format and Description
Shift Left Logical	SLL `rd`, `rt`, shamt Shift contents of register `rt` left by shamt bits, inserting zeroes into low order bits. Place 32-bit result in register `rd`.
Shift Right Logical	SRL `rd`, `rt`, shamt Shift contents of register `rt` right by shamt bits, inserting zeroes into high order bits. Place 32-bit result in register `rd`.
Shift Right Arithmetic	SRA `rd`, `rt`, shamt Shift contents of register `rt` right by shamt bits, sign-extending the high order bits. Place 32-bit result in register `rd`.
Shift Left Logical Variable	SLLV `rd`, `rt`, `rs` Shift contents of register `rt` left. Low-order 5-bits of register `rs` specify number of bits to shift. Insert zeroes into low order bits of `rt` and place 32-bit result in register `rd`.
Shift Right Logical Variable	SRLV `rd`, `rt`, `rs` Shift contents of register `rt` right. Low-order 5-bits of register `rs` specify number of bits to shift. Insert zeroes into high order bits of `rt` and place 32-bit result in register `rd`.
Shift Right Arithmetic Variable	SRAV `rd`, `rt`, `rs` Shift contents of register `rt` right. Low-order 5-bits of register `rs` specify number of bits to shift. Sign-extend the high order bits of `rt` and place 32-bit result in register `rd`.

Multiply and Divide Operations
Instruction	Format and Description
Multiply	MULT `rs`, `rt` Multiply contents of registers `rs` and `rt` as twos complement values. Place 64-bit result in special registers `HI`/`LO`
Multiply Unsigned	MULTU `rs`, `rt` Multiply contents of registers `rs` and `rt` as unsigned values. Place 64-bit result in special registers `HI`/`LO`
Divide	DIV `rs`, `rt` Divide contents of register `rs` by `rt` treating operands as twos complements values. Place 32-bit quotient in special register `LO`, and 32-bit remainder in `HI`.
Divide Unsigned	DIVU `rs`, `rt` Divide contents of register `rs` by `rt` treating operands as unsigned values. Place 32-bit quotient in special register `LO`, and 32-bit remainder in `HI`.
Move From `HI`	MF`HI` `rd` Move contents of special register `HI` to register `rd`.
Move From `LO`	MF`LO` `rd` Move contents of special register `LO` to register `rd`.
Move To `HI`	MT`HI` `rd` Move contents of special register `rd` to special register `HI`.
Move To `LO`	MT`LO` `rd` Move contents of register `rd` to special register `LO`.

Jump and branch instructions

Jump Instructions
Instruction	Format and Description
Jump	J target Shift 26-bit target address left two bits, combine with high-order 4-bits of PC and jump to address with a one instruction delay.
Jump and Link	JAL target Shift 26-bit target address left two bits, combine with high-order 4-bits of PC and jump to address with a one instruction delay. Place address of instruction following delay slot in `R31` (link register).
Jump Register	JR `rs` Jump to address contained in register `rs` with a one instruction delay.
Jump and Link Register	JALR `rs`, `rd` Jump to address contained in register `rs` with a one instruction delay. Place address of instruction following delay slot in `rd`.

Branch Instructions
Instruction	Format and Description
Branch on Equal	BEQ `rs`, `rt`, offset Branch to target address if register `rs` equal to `rt`
Branch on Not Equal	BNE `rs`, `rt`, offset Branch to target address if register `rs` not equal to `rt`.
Branch on Less than or Equal Zero	BLEZ `rs`, offset Branch to target address if register `rs` less than or equal to 0.
Branch on Greater Than Zero	BGTZ `rs`, offset Branch to target address if register `rs` greater than 0.
Branch on Less Than Zero	BLTZ `rs`, offset Branch to target address if register `rs` less than 0.
Branch on Greater than or Equal Zero	BGEZ `rs`, offset Branch to target address if register `rs` greater than or equal to 0.
Branch on Less Than Zero And Link	BLTZAL `rs`, offset Place address of instruction following delay slot in register R31 (link register). Branch to target address if register `rs` less than 0.
Branch on greater than or Equal Zero And Link	BGEZAL `rs`, offset Place address of instruction following delay slot in register R31 (link register). Branch to target address if register `rs` is greater than or equal to 0.

Branch Target: All Branch instruction target addresses are computed as follows: Add address of instruction in delay slot and the 16-bit offset (shifted left two bits and sign-extended to 32-bits). All branches occur with a delay of one instruction.

Special Instructions
Instruction	Format and Description
System Call	SYSCALL Initiates system call trap, immediately transferring control to exception handler. More information on the PSX SYSCALL routines are covered later on.
Breakpoint	BREAK Initiates breakpoint trap, immediately transferring control to exception handler.

More information on the PSX SYSCALL routines is covered later on.

Co-processor Instructions
Instruction	Format and Description
Load Wo`rd` to Co-processor	LWCz `rt`, offset (base) Sign-extend 16-bit offset and add to base to form address. Load contents of addressed word into co-processor register `rt` of co-processor unit z.
Store Wo`rd` from Co-processor	SWCz `rt`, offset (base) Sign-extend 16-bit offset and add to base to form address. Store contents of co-processor register `rt` from co-processor unit z at addressed memory word.
Move To Co-processor	MTCz `rt`, `rd` Move contents of CPU register `rt` into co-processor register `rd` of co-processor unit z.
Move from Co-processor	MFCz `rt`,`rd` Move contents of co-processor register `rd` from co-processor unit z to CPU register `rt`.
Move Control To Co-processor	CTCz `rt`,`rd` Move contents of CPU register `rt` into co-processor control register `rd` of co-processor unit z.
Move Control From Co-processor	CFCz `rt`,`rd` Move contents of control register `rd` of co-processor unit z into CPU register `rt`.
Move Control To Co-processor	COPz cofun Co-processor `z` performs an operation. The state of the R3000A is not modified by a co-processor operation.

System Control Co-processor (COP0) Instructions
Instruction	Format and Description
Move To CP0	MTC0 `rt`, `rd` Store contents of CPU register `rt` into register `rd` of CP0. This follows the convention of store operations.
Move From CP0	MFC0 `rt`, `rd` Load CPU register `rt` with contents of CP0 register `rd`.
Read Indexed TLB Entry	TLBR Load `EntryHi` and `EntryLo` registers with TLB entry pointed at by Index register.
Write Indexed TLB Entry	TLBWI Load TLB entry pointed at by Index register with contents of `EntryHi` and `EntryLo` registers.
Write Random TLB Entry	TLBWR Load TLB entry pointed at by Random register with contents of `EntryHi` and `EntryLo` registers.
Probe TLB for Matching Entry	TLBP Entry Load Index register with address of TLB entry whose contents match `EntryHi` and `EntryLo`. If no TLB entry matches, set high-order bit of Index register.
Restore From Exception	RFE Restore previous interrupt mask and mode bits of status register into current status bits. Restore old status bits into previous status bits.

R3000A opcode encoding

The following shows the opcode encoding for the MIPS architecture.

Opcode
Bits	28...26
38-29	0	1	2	3	4	5	6	7
0	SPECIAL	BCOND	J	JAL	BEQ	BNE	BLEZ	BGTZ
1	ADDI	ADDIU	SLTI	SLTIU	ANDI	ORI	XORI	LUI
2	COP0	COP1	COP2	COP3	-	-	-	-
3	-	-	-	-	-	-	-	-
4	LB	LH	LWL	LW	LBU	LHU	LWR	-
5	SB	SH	SWL	SW	-	-	SWR	-
6	LWC0	LWC1	LWC2	LWC3	-	-	-	-
7	SWC0	SWC1	SWC2	SWC3	-	-	-	-

Special
Bits	2-0
5-3	0	1	2	3	4	5	6	7
0	SLL	-	SRL	SRA	SLLV	-	SRLV	SRAV
1	JR	JALR	-	-	SYSCALL	BREAK	-	-
2	MFHI	MTHI	MFLO	MTLO	-	-	-	-
3	MULT	MULTU	DIV	DIVU	-	-	-	-
4	ADD	ADDU	SUB	SUBU	AND	OR	XOR	NOR
5	-	-	SLT	SLTU	-	-	-	-
6	-	-	-	-	-	-	-	-
7	-	-	-	-	-	-	-	-

`BCOND`
Bits	8-16
20-19	0	1	2	3	4	5	6	7
0	BLTZ	BGEZ
1
2	BLTZAL	BGEZAL

`COPz`
Bits	23-21
25-24	0	1	2	3	4	5	6	7
0	MF		CF		MT		CT
1	BC	-	-	-	-	-	-	-

Co-Processor Specific Operations

`COP0`
Bits	2-0
4-3	0	1	2	3	4	5	6	7
0		TLBR	TLBWI				TLBWR
1	TLBP
2	RFE
3

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